1. Field of the Invention
The present invention relates to boosting circuits for boosting the power-supply voltage, and particularly to a word line boosting circuit for generating a voltage in reading operation in a semiconductor storage device having semiconductor non-volatile memory elements.
2. Description of the Background Art
In these years, there is a growing trend toward use of lower power-supply voltages in semiconductor devices in order to reduce the dissipation of power or for another purpose. Also, some semiconductor devices may be required to allow for a wide range between the upper and lower limits of the power-supply voltage. Moreover, in applications of semiconductor devices to various products, the specifications of the required permissible range of the power-supply voltage may differ depending on the product type.
The use of lower, and an increasing variety of, power-supply voltage values are demanded also for semiconductor storage devices having semiconductor non-volatile memory elements such as flash memory elements. In the semiconductor non-volatile memory elements, however, simply lowering the power-supply voltage will increase the read time and thus hinder high-speed operation.
Accordingly such semiconductor storage devices require word line boosting circuits for boosting the word line voltage from the power-supply voltage in reading operation. The word line boosting circuits are required to operate only when needed, e.g. during reading operation, and to be inactive in other states, e.g. during standby state, so as not to waste power.
Now, FIG. 29 shows an example of the configuration of a semiconductor storage device having semiconductor non-volatile memory elements. In FIG. 29, the semiconductor storage device has a memory cell array AR, a data input/output buffer DB for buffering data signals D0 to Dk inputted/outputted to and from the memory cell array AR, and an address buffer AB for buffering address signals A0 to Aj for addressing locations in the memory cell array AR. The memory cell array AR includes a plurality of cells regularly arranged therein, each memory cell including a selecting transistor ST and a pair of semiconductor non-volatile memory elements ME1 and ME2.
In each cell, the semiconductor non-volatile memory elements ME1 and ME2 have their respective drains connected to the source of the selecting transistor ST through an interconnection DL. A gate select line GL is connected to the gate of the selecting transistor ST and a bit line BL0 is connected to its drain. Word lines WLa and WLb are connected to the control gates of the semiconductor non-volatile memory elements ME1 and ME2, and a source line SL is connected to the sources of the two elements. A body line BD is connected to the bodies of the semiconductor non-volatile memory elements ME1 and ME2. A plurality of such cells are arranged in the row direction to form the blocks B0 to Bn and the blocks B0 to Bn are arranged in the column direction to form the memory cell array AR.
A row decoder XD and a column decoder YD are connected to the address buffer AB. Further, a control block CB including a column selecting circuit, a sense amplifier and a page buffer is connected to the column decoder YD. The control block CB is connected also to the data input/output buffer DB. The gate select line GL, word lines WLa and WLb, source line SL and body line BD connected to the cells in the blocks B0 to Bn in the memory cell array AR extend from the row decoder XD. Bit lines BL0 to BLm connected to a plurality of cells in the memory cell array AR across the blocks B0 to Bn extend from the control block CB.
The semiconductor storage device further comprises a microprocessor MP for controlling write and erase of information into and from the semiconductor non-volatile memory elements ME1 and ME2, a positive charge pump circuit CPp for generating a positive high voltage and a negative charge pump circuit CPn for generating a negative high voltage, which are controlled by the microprocessor MP. It further comprises a word line boosting circuit BC for generating a high voltage on the word lines in operation of reading the stored contents. These high-voltage generating circuits operate only when needed, and become inactive in other operations such as standby operation so as not to consume wasteful power.
The outputs of the positive charge pump circuit CPp, negative charge pump circuit CPn and the word line boosting circuit BC are all inputted to a voltage select circuit VS. The voltage select circuit VS gives a positive high voltage for writing to the circuits in the control block CB through a voltage signal line VL1 and also gives a positive or negative high voltage for writing, erasing and reading to the row decoder XD through voltage signal lines VL2.
In this semiconductor storage device, the present invention focuses on the word line boosting circuit BC. In the semiconductor storage device having semiconductor non-volatile memory elements, what is required for the word line boosting circuit BC is not simple generation of a high voltage. This is described referring to FIG. 30.
FIG. 30 is a diagram showing threshold voltages required for channel formation in mass-produced semiconductor non-volatile memory elements and a distribution thereof. In FIG. 30, the horizontal axis shows the threshold voltage VTH and the vertical axis shows the distribution D (VTH).
In the case of an N-channel semiconductor non-volatile memory element, for example, its threshold voltage rises when electrons are injected to a floating electrode. In this example, a state in which electrons are injected to the floating electrode is regarded as xe2x80x9c1xe2x80x9d and a state in which electrons are not is regarded as xe2x80x9c0.xe2x80x9d The threshold voltage corresponding to xe2x80x9c1xe2x80x9d and the threshold voltage corresponding to xe2x80x9c0xe2x80x9d differ in different semiconductor non-volatile memory elements, which form a distribution as shown in FIG. 30. The threshold voltage corresponding to xe2x80x9c0xe2x80x9d of the semiconductor non-volatile memory elements is set in the viewpoint of high-speed access and the threshold voltage corresponding to xe2x80x9c1xe2x80x9d is set in the viewpoint of securing read margin and reliability.
The values xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d of the semiconductor non-volatile memory elements are distinguished according to whether the threshold voltage is higher or lower than a reference voltage Vbs. Hence, if the value of the reference voltage Vbs is lower than the upper limit value V1 of the distribution of the threshold voltages corresponding to xe2x80x9c0,xe2x80x9d then xe2x80x9c0xe2x80x9d may be erroneously determined to be xe2x80x9c1.xe2x80x9d Similarly, if the value of the reference voltage Vbs is higher than the lower limit value V2 of the distribution of the threshold voltages corresponding to xe2x80x9c1,xe2x80x9d then xe2x80x9c1xe2x80x9d may be erroneously determined to be xe2x80x9c0.xe2x80x9d Therefore the reference voltage Vbs for determining the threshold voltage level must fall between the upper limit value V1 and the lower limit value V2. That is to say, although the word line boosting circuit BC boosts the power-supply voltage, it should not boost it too high.
FIG. 31 is a diagram showing a conventional word line boosting circuit BCe. The word line boosting circuit BCe operates with a boost enable signal BE to generate the boosted voltage Vbs; it gives voltages boosted in the two boosting circuits HCe and VCe to the N-channel MOS transistor TR1. The word line boosting circuit BCe further comprises delay circuits D1 and D2, a NOR gate NOG1, a NAND gate NAG1, and inverters Ih1, Ih2, Iv1 and Iv2.
The boost enable signal BE is inputted to the delay circuits D1 and D2 and also to input ends of the NOR gate NOG1 and NAND gate NAG1. The output DL1 of the delay circuit D1 is inputted to the other input end of the NOR gate NOG1 and the output DL2 of the delay circuit D2 is inputted to the other input end of the NAND gate NAG1.
The output of the NOR gate NOG1 passes through the inverter Ih1 to become a gate boost enable signal HBE and the gate boost enable signal HBE further passes through the inverter Ih2 to become an inverse gate boost enable signal BHBE. The inverse gate boost enable signal BHBE is inputted to the gate boosting circuit HCe.
The output of the NAND gate NAG1 passes through the inverter Iv1 to become a drain boost enable signal VBE and the drain boost enable signal VBE further passes through the inverter Iv2 to become an inverse drain boost enable signal BVBE. The inverse drain boost enable signal BVBE is inputted to the drain boosting circuit VCe.
The output HB of the gate boosting circuit HCe is given to the gate of the transistor TR1 and the output VB of the drain boosting circuit VCe is given to the drain of the transistor TR1. The transistor TR1 turns on when the output HB is applied to its gate and the voltage of the output VB at the drain is applied to a load connected to the source of the transistor TR1.
In this structure, the gate boosting circuit HCe and the drain boosting circuit VCe have structures as shown in FIG. 32. That is to say, the gate boosting circuit HCe has a plurality of boosting stages SGh1e to SGh4e connected in series, where the first boosting stage SGh1e receives the inverse gate boost enable signal BHBE from the inverter Ih2 and the final boosting stage SGh4e generates the output HB. Although this example shows four boosting stages, it may include a larger or a smaller number of stages.
The drain boosting circuit VCe has a plurality of boosting stages SGv1e to SGv3e connected in series, where the first boosting stage SGv1e receives the inverse drain boost enable signal BVBE from the inverter Iv2 and the final boosting stage SGv3e generates the output VB. Although this example shows three boosting stages, it may include a larger or a smaller number of stages.
However, note that it is preferred that the gate boosting circuit HCe should have a slightly larger number of boosting stages than the drain boosting circuit VCe. That is, when the voltage value of the output HB of the gate boosting circuit HCe is sufficiently high and a sufficiently high voltage is applied to the gate of the transistor TR1, then the voltage value of the output VB of the drain boosting circuit VCe can be outputted as the boosted voltage Vbs. If the voltage value of the output HB of the gate boosting circuit HCe is low, the voltage value obtained as the boosted voltage Vbs stays around the output HB minus the threshold voltage of the transistor TR1.
In the gate boosting circuit HCe, while the first boosting stage SGh1e receives only the inverse gate boost enable signal BHBE, the next and following boosting stages SGh2e to SGh4e receive the inverse gate boost enable signal BHBE and also an output from the preceding stage and they each boost the output from the preceding stage using the inverse gate boost enable signal BHBE. Similarly, in the drain boosting circuit VCe, the first boosting stage SGv1e receives only the inverse drain boost enable signal BVBE, but the next and following boosting stages SGv2e and SGv3e receive the inverse drain boost enable signal BVBE and also an output from the preceding stage and they each boost the output from the preceding stage using the inverse drain boost enable signal BVBE.
Now the configuration of the boosting stages is described. The boosting stages in the gate boosting circuit HCe and the drain boosting circuit VCe adopt the unit boosting stages shown below.
FIG. 33 is a diagram showing a specific configuration of a unit boosting stage SGa adopted as the first boosting stages SGh1e and SGv1e. The unit boosting stage SGa has a CMOS connection of a P-channel MOS transistor P11 and an N-channel MOS transistor N11, a CMOS connection of a P-channel MOS transistor P12 and an N-channel MOS transistor N12, a capacitor C1 and a P-channel MOS transistor P13.
That is to say, in the unit boosting stage SGa, the gates of the transistors P11 and N11 are connected to each other and the inverse gate boost enable signal BHBE or inverse drain boost enable signal BVBE is applied there. A power-supply voltage Vcc is applied to the source of the transistor P11 and a ground voltage GND is applied to the source of the transistor N11. The drains of the transistors P11 and N11 are connected to each other and one end (a first end) of the capacitor C1 is connected there.
The transistors P12 and N12 have their respective gates connected to each other, and the inverse gate boost enable signal BHBE or inverse drain boost enable signal BVBE is applied there. The other end (a second end) of the capacitor C1 is connected to the source of the transistor P12 and the ground voltage GND is given to the source of the transistor N12. The transistors P12 and N12 have their respective drains connected to the each other and the gate of the transistor P13 is connected there.
The second end of the capacitor C1 is connected also to the drain of the transistor P13, and the voltage in this portion becomes the output Vouta of the unit boosting stage SGa. The power-supply voltage Vcc is given to the source of the transistor P13. The bodies of the transistors P11 to P13 are connected to their respective sources.
FIG. 34 is a diagram showing a specific configuration of a unit boosting stage SGb adopted in the second and following boosting stages SGh2e to SGh4e and SGv2e and SGv3e. The unit boosting stage SGb has a CMOS connection of a P-channel MOS transistor P21 and an N-channel MOS transistor N21, a CMOS connection of a P-channel MOS transistor P22 and an N-channel MOS transistor N22, a capacitor C2 and a P-channel MOS transistor P23.
That is to say, in the unit boosting stage SGb, the gates of the transistors P21 and N21 are connected to each other and the inverse gate boost enable signal BHBE or inverse drain boost enable signal BVBE is applied there. An input Vina corresponding to an output from the preceding stage is given to the source of the transistor P21 and the ground voltage GND is given to the source of the transistor N21. The drains of the transistors P21 and N21 are connected to each other, to which one end (a first end) of the capacitor C2 is connected.
The transistors P22 and N22 have their respective gates connected to each other, and the inverse gate boost enable signal BHBE or inverse drain boost enable signal BVBE is given there. The other end (a second end) of the capacitor C2 is connected to the source of the transistor P22 and the ground voltage GND is given to the source of the transistor N22. The transistors P22 and N22 have their respective drains connected to each other and the gate of the transistor P23 is connected thereto.
The second end of the capacitor C2 is connected also to the drain of the transistor P23, and the voltage in this portion becomes the output Voutb of the unit boosting stage SGb. The power-supply voltage Vcc is given to the source of the transistor P23. The bodies of the transistors P21 to P23 are connected to their respective sources.
Operation of this word line boosting circuit BCe is now described. FIG. 35 is a timing chart of signal outputs from the individual parts. In this timing chart, the operation of the word line boosting circuit BCe is divided into a setup period for charging the capacitors C1 and C2 and a boost period for giving the boosted voltage to a load connected to the source of the transistor TR1.
First, in response to an ATD (Address Transition Detection) signal generated by a change of the address signal ADD in reading of the stored contents, the boost enable signal BE (e.g. high-active) becomes inactive. The inactive period PD1 of the boost enable signal BE is about 20 ns, for example. The inactivated change of the boost enable signal BE corresponds to the beginning of the setup period.
The change to inactive of the boost enable signal BE is sequentially transferred through the NOR gate NOG1 and the inverter Ih1 while being delayed in the delay circuit D1, and it changes the gate boost enable signal HBE, reflecting the amount of delay in the delay circuit D1. In FIG. 35, the total amount of delays in the delay circuit D1, NOR gate NOG1 and inverter Ih1 is shown as delay 3.
The change to inactive of the boost enable signal BE is sequentially transferred through the NAND gate NAG1 and the inverter Iv1 while being delayed in the delay circuit D2. However, in the NAND gate NAG1, the inactivated change of the boost enable signal BE immediately appears as a change in the output, so that it changes the drain boost enable signal VBE without reflecting the amount of delay in the delay circuit D2. However, the delay circuit D2, NAND gate NAG1 and inverter Iv1 each cause a slight gate delay; FIG. 35 shows the total amount of delays in the delay circuit D2, NAND gate NAG1 and inverter Iv1 as delay 0.
The change of the gate boost enable signal HBE passes through the inverter Ih2 to change the inverse gate boost enable signal BHBE, which change is transferred to the boosting stages in the gate boosting circuit HCe. First, in the first stage SGh1e, the transistor N11 becomes conductive and gives the ground voltage GND to the first end of the capacitor C1. Further, the transistor N12 becomes conductive and gives the ground voltage GND to the gate of the transistor P13. When the transistor P13 becomes conductive, the power-supply voltage Vcc is given to the second end of the capacitor C1. The capacitor C1 is thus charged.
When the transistor P13 becomes conductive, the power-supply voltage Vcc is given also as the output Vouta of the first stage SGh1e. Then the input Vina to the next stage SGh2e becomes equal to the power-supply voltage Vcc. Like the capacitor C1, the capacitor C2, too, is supplied with the ground voltage GND at its one end (a first end) and the power-supply voltage Vcc at the other end (a second end). The capacitor C2 is thus charged.
The same takes place also in the following boosting stages SGh3e and SGh4e and the capacitors in these stages are thus charged. Therefore the power-supply voltage Vcc appears at the output HB of the gate boosting circuit HCe at this time.
This applies also to the boosting stages in the drain boosting circuit VCe; FIG. 35 shows the condition in which the output HB of the gate boosting circuit HCe and the output VB of the drain boosting circuit VCe are both brought back to the power-supply voltage Vcc in the setup period.
When the boost enable signal BE goes active, the change is sequentially transferred through the NOR gate NOG1 and the inverter Ih1 while being delayed in the delay circuit D1. However, in the NOR gate NOG1, the activated change of the boost enable signal BE immediately appears as a change in the output, so that it changes the gate boost enable signal HBE without reflecting the amount of delay in the delay circuit D1. However, the delay circuit D1, NOR gate NOG1 and inverter Ih1 each cause a slight gate delay; FIG. 35 shows the total amount of delays in the delay circuit D1, NOR gate NOG1 and inverter Ih1 as delay 1.
The activated change of the boost enable signal BE is sequentially transferred through the NAND gate NAG1 and the inverter Iv1 while being delayed in the delay circuit D2, and it changes the gate boost enable signal HBE, reflecting the amount of delay in the delay circuit D2. In FIG. 35, the total amount of delays in the delay circuit D2, NAND gate NAG1 and inverter Iv1 is shown as delay 2.
The change of the gate boost enable signal HBE passes through the inverter Ih2 and changes the inverse gate boost enable signal BHBE, which change is transferred to the boosting stages in the gate boosting circuit HCe. First, in the first stage SGh1e, the transistor P12 becomes conductive and the transistor P13 turns off, and the potential at the second end of the capacitor C1 goes in a floating state. Since the capacitor C1 was being charged till a moment before, the voltage Vcc is occurring between both ends thereof.
The transistor P11 becomes conductive and the power-supply voltage Vcc is given to the first end of the capacitor C1. Then the voltage at the second end of the capacitor C1 in the floating state becomes 2Vcc. Therefore the output Vouta of the first stage SGh1e becomes 2Vcc.
The input Vina to the second stage SGh2e becomes 2Vcc, and the voltage Vcc is occurring between both ends of the capacitor C2 as in the capacitor C1, so the output Voutb of the second stage SGh2e becomes 3Vcc.
The same occurs in the following boosting stages SGh3e and SGh4e and the voltage has been thus boosted in each stage. Therefore a voltage at 5Vcc, which has been boosted five times the power-supply voltage Vcc, appears as the output HB of the gate boosting circuit HCe. The actual voltage value appearing as the output HB is smaller than 5Vcc because of the parasitic capacitance between the source and drain of the transistors in each boosting stage, the interconnection capacitance at the output HB, the gate capacitance of the transistor TR1, etc.
This occurs also in the boosting stages in the drain boosting circuit VCe, where a voltage of 4Vcc, which has been boosted four times the power-supply voltage Vcc, appears as the output VB of the drain boosting circuit VCe. As stated before, it is desired that the value of the output HB be boosted larger with a sufficient margin MG than the value of the output VB. The value of the margin MG may be 1.5 V or more, for example. The beginning of the boost of the output VB of the drain boosting circuit VCe is the end of the setup period and the start of the boost period.
The timing of the signal transitions is shifted between the gate boost enable signal HBE and the drain boost enable signal VBE using the delay circuits D1 and D2, NOR gate NOG1 and NAND gate NAG1 for the following reason.
The boost in the drain boosting circuit VCe is delayed behind the boost in the gate boosting circuit HCe through the presence of the period xe2x80x9cdelay 2xe2x80x9d for the reason below. That is to say, the drain and source of the transistor TR1 are made to conduct while the output VB is at the power-supply voltage Vcc so as to start the boost after once setting the voltage of the load connected to the source of the transistor TR1 at the power-supply voltage Vcc.
The setup in the gate boosting circuit HCe is delayed behind the setup in the drain boosting circuit VCe through the presence of the period xe2x80x9cdelay 3xe2x80x9d for the reason below. That is to say, the setup of the drain boosting circuit VCe is started while the output HB is being boosted and the drain and source of the transistor TR1 are conducting, so as to electrically disconnect the transistor TR1 and the load connected to the source of the transistor TR1 after drawing off the charge of the load to a certain extent with the transistor N22. FIG. 36 shows an equivalent circuit of the word line boosting circuit BCe during boosting. FIG. 36 shows the number of unit boosting stages in the drain boosting circuit VCe as Nv and the capacitors in the unit boosting stages as Cv1 to CvNv. The load connected to the source of the transistor TR1 is shown as capacitance CvLD.
The relation between the boosted voltage Vbs and the power-supply voltage Vcc is now expressed in equations by using this equivalent circuit. First, assuming that the transistor TR1 is off, the voltages in the individual parts during boosting are given as:
VB=(Nv+1)xc3x97Vccxe2x80x83xe2x80x831
Vbs=Vccxe2x80x83xe2x80x832
Since the transistor TR1 turns on in real boosting, redistribution of charge occurs between the capacitors Cv1 to CvNv and the load capacitance CvLD. Now, considering the conservation of charge, the equation below holds:                                                         Cvboost              Nv                        ⁢                          {                                                                    (                                          Nv                      +                      1                                        )                                    xc3x97                  Vcc                                -                Vcc                            }                                +                      Cvload            xc3x97            Vcc                          =                                            Cvboost              Nv                        ⁢                          (                              Vbs                -                Vcc                            )                                +                      Cvload            xc3x97            Vbs                                      3      
The left side expresses the amount of charge on the xe2x80x9coffxe2x80x9d assumption and the right side expresses the amount of charge on the xe2x80x9conxe2x80x9d assumption. Cvboost indicates the capacitance value of each of the capacitors Cv1 to CvNv and Cvload indicates the capacitance value of the load capacitance CvLD.
Equation 3 can be rearranged as:
xe2x80x83(Nvxc3x97Cvload+Cvboost)xc3x97Vbs={Nvxc3x97Cvload+(Nv+1)xc3x97Cvboost}xc3x97Vccxe2x80x83xe2x80x834
Equation 4 can be rearranged as:                     Vbs        =                                                            Nv                xc3x97                Cvload                            +                                                (                                      Nv                    +                    1                                    )                                xc3x97                Cvboost                                                                    Nv                xc3x97                Cvload                            +              Cvboost                                xc3x97          Vcc                            5      
As can be seen from Equation 5, the boosted voltage Vbs is proportional to the power-supply voltage Vcc. Equation 5 can be represented in the graph of FIG. 37.
In FIG. 37, the range of the power-supply voltage Vcc used in the semiconductor device is expressed as the range from the lower limit Vccmin to the upper limit Vccmax. The graph also shows, on the axis of the boosted voltage Vbs, the upper limit value V1 of the above-described threshold voltage distribution corresponding to xe2x80x9c0xe2x80x9d of the semiconductor non-volatile memory elements and the lower limit value V2 of the threshold voltage distribution corresponding to xe2x80x9c1.xe2x80x9d
As stated before, the boosted voltage Vbs must be larger than the upper limit value V1 and smaller than the lower limit value V2. The value of the power-supply voltage Vcc which satisfies this condition is limited within the range xe2x80x9cOKxe2x80x9d shown in FIG. 37. That is to say, in the range between the lower limit Vccmin and the upper limit Vccmax, boosted voltages in the range xe2x80x9cNG1xe2x80x9d below the range xe2x80x9cOKxe2x80x9d cause failure to comply with the specifications by the shortage of voltage AM1 and boosted voltages in the range xe2x80x9cNG2xe2x80x9d over the range xe2x80x9cOKxe2x80x9d cause failure to comply with the specifications by the excess of voltage AM2.
This cannot be solved just by changing the gradient of the graph of FIG. 37 by adjusting various parameters in Equation 5. For example, the range xe2x80x9cNG1xe2x80x9d under the upper limit value V1 can be made smaller by making the graph steeper. However, this enlarges the range xe2x80x9cNG2xe2x80x9d over the lower limit value V2. On the other hand, making the gradient of the graph gentler to make the range xe2x80x9cNG2xe2x80x9d smaller enlarges the range xe2x80x9cNG1.xe2x80x9d
In this way, the conventional word line boosting circuit has been restricted in that the value of the power-supply voltage Vcc must be such that the boosted voltage Vbs falls within the range between the upper limit value V1 and the lower limit value V2 of the threshold voltage distribution of the semiconductor non-volatile memory elements. Accordingly they have been subjected to restriction when the range between the upper and lower limits of the permissible power-supply voltage range required for the semiconductor device is large and when the specifications of the required permissible power-supply voltage range differ product by product.
For example, when one type of product requires 1.65 to 2.2 V as the characteristic of the power-supply voltage, another type of product may require 2.2 to 2.7 V as the power-supply voltage characteristic, and still another type of product may require 2.7 to 3.6 V as the power-supply voltage characteristic. In such a case, semiconductor storage devices adopting the conventional word line boosting circuit had to be adjusted by varying the number of boosting stages and the capacitance value of the capacitors in the boosting stages, depending on the product type. More specifically, it has been necessary to prepare photomasks for photolithography for each product type and to pattern the photomasks in accordance with the product type.
However, preparing photomasks for each product type unavoidably leads to an increase in cost.
According to a first aspect of the present invention, a boosting circuit comprises: a detecting portion for detecting the value of a power-supply voltage; and a first boosting stage comprising a plurality of capacitors, for boosting the power-supply voltage using at least one of the plurality of capacitors, wherein the detecting portion determines, in accordance with the detected value of the power-supply voltage, whether to use one of the plurality of capacitors alone in the first boosting stage or to use a parallel connection of some or all of the plurality of capacitors.
Preferably, according to a second aspect, the boosting circuit further comprises a transistor having first and second current electrodes and a control electrode, and a second boosting stage comprising a capacitor, for boosting the power-supply voltage by using the capacitor, wherein the first boosting stage applies the power-supply voltage as boosted to the first current electrode of the transistor, and the second boosting stage applies the power-supply voltage as boosted to the control electrode of the transistor.
Preferably, according to a third aspect, the boosting circuit further comprises a transistor having first and second current electrodes and a control electrode, and a second boosting stage comprising a capacitor, for boosting the power-supply voltage by using the capacitor, wherein the first boosting stage applies the power-supply voltage as boosted to the control electrode of the transistor, and the second boosting stage applies the power-supply voltage as boosted to the first current electrode of the transistor.
According to a fourth aspect of the present invention, a boosting circuit comprises: a detecting portion for detecting the value of a power-supply voltage; and a plurality of boosting stages each comprising a capacitor, for boosting the power-supply voltage by using the capacitor, wherein the plurality of boosting stages are connected in series, and the detecting portion determines which output of the plurality of boosting stages should be used in accordance with the detected value of the power-supply voltage.
Preferably, according to a fifth aspect, the boosting circuit further comprises a transistor having first and second current electrodes and a control electrode, and the boosting stages apply the power-supply voltage as boosted to the first current electrode of the transistor.
Preferably, according to a sixth aspect, the boosting circuit further comprises a transistor having first and second current electrodes and a control electrode, and the boosting stages apply the power-supply voltage as boosted to the control electrode of the transistor.
According to a seventh aspect of the present invention, a boosting circuit comprises: a detecting portion for detecting the value of a power-supply voltage; a transistor having first and second current electrodes and a control electrode; and first and second boosting stages each comprising a capacitor, for boosting the power-supply voltage by using the capacitor, wherein the first boosting stage applies the power-supply voltage as boosted to the first current electrode of the transistor, the second boosting stage applies the power-supply voltage as boosted to the control electrode of the transistor, and the detecting portion varies the amount of boost in the first or second boosting stage in accordance with the detected value of the power-supply voltage.
Preferably, according to an eighth aspect, the boosting circuit is used as a word line boosting circuit in a semiconductor storage device comprising a semiconductor non-volatile memory element, a word line connected to the semiconductor non-volatile memory element, and the word line boosting circuit for reading the contents stored in the semiconductor non-volatile memory element through the word line.
According to a ninth aspect of the present invention, a semiconductor storage device comprises: a semiconductor non-volatile memory element, a word line connected to the semiconductor non-volatile memory element, and a word line boosting circuit for reading the contents stored in the semiconductor non-volatile memory element through the word line, wherein the word line boosting circuit is constructed from one of the boosting circuits of the first aspect to the seventh aspect.
According to the first aspect of the invention, the detecting portion determines whether to use only one of the plurality of capacitors in the first boosting stage or to use a parallel connection of some or all of the plurality of capacitors, in accordance with the detected value of the power-supply voltage. Accordingly power-supply voltages over a wide magnitude range can be used while generating the boosted voltage within the range between the upper and lower limit values of the threshold voltage distribution of semiconductor non-volatile memory elements.
According to the second aspect of the invention, the first boosting stage applies the boosted power-supply voltage to the first current electrode of the transistor. Accordingly, when a load is connected to the second current electrode of the transistor, a large voltage can be generated between both ends of the load.
According to the third aspect of the invention, the first boosting stage applies the boosted power-supply voltage to the control electrode of the transistor. Accordingly, when a load is connected to the second current electrode of the transistor, a large voltage can be generated between both ends of the load.
According to the fourth aspect of the invention, the detecting portion determines, in accordance with the detected value of the power-supply voltage, which output to use among the outputs from the plurality of boosting stages. Accordingly power-supply voltages of various magnitudes can be used while generating the boosted voltage within the range between the upper and lower limit values of the threshold voltage distribution of semiconductor non-volatile memory elements.
According to the fifth aspect of the invention, the boosting stages apply the boosted power-supply voltage to the first current electrode of the transistor. Accordingly, when a load is connected to the second current electrode of the transistor, a large voltage can be generated between both ends of the load.
According to the sixth aspect of the invention, the boosting stages apply the boosted power-supply voltage to the control electrode of the transistor. Accordingly, when a load is connected to the second current electrode of the transistor, a large voltage can be generated between both ends of the load.
According to the seventh aspect of the invention, the detecting portion varies the amount of boosting in the first or second boosting stage in accordance with the detected value of the power-supply voltage. Accordingly power-supply voltages over a wide magnitude range can be used while generating the boosted voltage within the range between the upper and lower limit values of the threshold voltage distribution of semiconductor non-volatile memory elements. Further, when a load is connected to the second current electrode of the transistor, a large voltage can be generated between both ends of the load.
According to the eighth aspect of the invention, the word line boosting circuit is composed of any of the boosting circuits of the first to seventh aspects of the invention. Therefore it is possible to obtain a semiconductor storage device which can use power-supply voltages of various magnitudes while generating the boosted voltage within the range between the upper and lower limit values of the threshold voltage distribution of the semiconductor non-volatile memory elements.
An object of the present invention is to provide a word line boosting circuit which, regardless of varying value of the power-supply voltage, can generate a boosted voltage within the range between the upper and lower limit values of the threshold voltage distribution of semiconductor non-volatile memory elements.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.